Field-effect transistors include source, drain and gate structures. A biasing voltage applied across gate and source terminals allows the flow of charge carriers, namely electrons or holes, between source and drain. Junction field-effect transistors (JFETs) are characterized by doped channel regions and ohmic contacts forming the source and drain regions.
Active matrix devices such as displays (e.g. televisions, laptop monitors), imagers (e.g. x-ray imagers) and sensors typically use hydrogenated amorphous silicon (a-Si:H) and, in some applications, low-temperature poly-silicon (LTPS) thin-film transistor (TFT) backplanes on glass or, for flexible devices, clear plastic. However, for very high resolution applications (>1000 pixels per inch (ppi)), such as micro-displays or pico-projectors, the carrier mobility of a-Si:H (electron mobility of about 1 cm2/Vs) is too low to provide sufficient drive current at short TFT channel widths. For applications requiring high drive current, such as active matrix organic light emitting diode (AMOLED) displays, it is necessary to shrink the gate length and/or increase the gate width of a-Si:H transistors. This leads to increasing the processing cost of a-Si:H active matrix circuits due to the relatively small gate lengths as well as a significant trade-off in display resolution due to larger gate widths. LTPS is more expensive than a-Si:H, but capable of providing higher drive currents. The device-to-device variation of threshold voltage and mobility in LTPS transistors requires compensation circuitry that limits the resolution of the active matrix. Single crystalline silicon (c-Si) has been used as an alternative for very high resolution backplanes, but processing c-Si can require high temperatures not compatible with glass substrates currently used in manufacturing a-Si:H or LTPS devices or clear plastic substrates that may be used.
Some existing displays have pixel densities of about 100 PPI (pixels per inch), each pixel including three RGB sub-pixels. Pixel dimensions of such devices may be about one hundred microns (100 μm). Such displays further include organic light emitting diodes (OLEDs) requiring a drive current of about 300 nA for a 100 μm pixel. Amorphous hydrogenated silicon thin film transistors (TFTs) having standard SiNx gate dielectrics are employed in conjunction with the OLEDs. Using such TFTs, resolutions greater than 150 PPI are difficult.
FIGS. 25A and 25B schematically illustrate amorphous hydrogenated silicon (a-Si:H) TFTs. The transistor 40 shown in FIG. 25A is back-channel etched and the transistor 60 shown in FIG. 25B is back-channel passivated. Both transistors 40, 60 are bottom-gate structures having undoped a-Si:H channels 42. Source/drain structures 44, gates 46 and gate dielectric (nitride) layers 48 are operatively associated with the channels. The gates 46 adjoin the substrate 50. In the embodiment of FIG. 25B, a nitride passivation layer 52 is formed on the channel layer 42. As the channels 42 are undoped, the source/channel/drain of each transistor forms an n/i/n junction. The off-current of the transistors is low partly due to hole mobility being much smaller than electron mobility. The low TFT mobility (less than 1 cm2/Vs), however, limits the TFT application for high drive current and/or low voltage applications. The transistors 40, 60 are accordingly more suited for use as switching TFTs than driver TFTs in active matrix circuits. Poly-Si has higher mobility, but also higher off-current and can suffer from device-to-device threshold voltage (VT) variation.